1. Field of the Invention
The present invention relates to a method and apparatus for generating a reference signal and, more particularly, to generating a low-voltage reference signal for integrated circuits such as memory devices.
2. State of the Art
Dynamic random access memory (DRAM) devices provide a relatively inexpensive way to provide a large system memory. DRAM devices are relatively inexpensive because, in part, as compared to other memory technologies, a typical single DRAM cell consists only of two components: an access transistor and a capacitor. The access transistor is typically a metal oxide (MOS) transistor having a gate, a drain, and a source, as will be understood by those skilled in the art. The capacitor, which stores a high or low voltage representing high and low data bits, respectively, is coupled between the drain of the access transistor and a cell plate charged to Vcc/2. The gate of the access transistor is coupled to a word line and the source is coupled to a digit line. Thus, activating the word line turns on the transistor, coupling the capacitor to the digit line and thereby enabling data to be read from the DRAM cell by sensing the voltage at the digit line. Data is written to the DRAM cell by applying a desired voltage to the digit line.
DRAM technology is an inherently transitory nature storage technology. As is well known in the art, the storage capability of the DRAM cell is transitory in nature because the charge stored on the capacitor leaks. The charge can leak, for example, across the plates of the capacitor or out of the capacitor through the access transistor. The leakage current through a MOS transistor is an unwanted current flowing from drain to source even when the gate-to-source voltage of the transistor is less than the threshold voltage, as will be understood by those skilled in the art. As a result, DRAM cells must be refreshed many times per second to preserve the stored data. With the refresh process being repeated many times per second, an appreciable quantity of power is consumed. In portable systems, obtaining the longest life out of the smallest possible battery is a crucial concern, and, therefore, reducing the need to refresh memory cells and, hence, reducing power consumption is highly desirable.
The refresh time of a memory cell is degraded by two major types of leakage; current junction leakage current caused by defects at the junction boundary of the transistor and channel leakage current caused by sub-threshold current flowing through the transistor. The junction leakage current may be reduced by decreasing the channel implantation dose which may undesirably cause an increase in the channel leakage. Similarly, the sub-threshold current may be reduced by increasing the threshold voltage of the transistor which may cause an increase in the junction leakage current.
A negatively biased word line scheme has been devised to reduce both the junction leakage current and the channel leakage current at the same time. In such an approach, the memory device employing a negative word line scheme applies a negative voltage of typically −0.5 to −0.2 volts to the word lines of the non-selected memory cells.
As stated, the need to refresh memory cells can be reduced by reducing current leakage through the access transistor by increasing the threshold voltage of the access transistor. The semiconducting materials comprising the DRAM cells can be doped to increase the threshold voltage to activate the transistor from a typical level of 0.6 volts to 1.0 or more volts. Increasing the threshold voltage, because of the field effects in the MOS transistors used in typical DRAM cells, reduces the magnitude of current leakage through the access transistor. This is true because, as will be understood by those skilled in the art, when the polarity of the applied gate-to-source voltage causes the transistor to turn OFF, current decreases as the difference between the applied gate-to-source-voltage and threshold voltage increase. Thus, for a given voltage applied on a word line to turn OFF the corresponding access transistors, an increase in the threshold voltage will decrease the leakage current of the transistor for that word line voltage.
Increasing threshold voltage to suppress current leakage, however, becomes a less optimal solution as memory cells are reduced to fit more and more memory cells on a single die. This is because, for example, miniaturization of memory cells results in cell geometries that render the cells vulnerable to damage as higher voltages are applied.
Instead of increasing the threshold voltage of the access transistor and leaving the applied word line voltage the same, leakage current can be reduced by increasing the magnitude of the gate-to-source voltage that is applied to turn OFF the access transistor and leaving the threshold voltage of the transistor the same. Thus, instead of applying zero volts on the word line to turn OFF an NMOS access transistor, a negative voltage of −0.3 volts may be applied to the word line, decreasing the transistor's current leakage for a given threshold voltage.
The application of a negative voltage to the word line must be precisely controlled or the channel of the pass gate which isolates the storage capacitor may be significantly stressed or completely damaged. Therefore, a stable and accurate voltage reference has been conventionally employed for generating a negative voltage word line (VNWL) signal. Desirably, precision voltage references should be insensitive to variations in process (P), temperature (T) and supply voltage (V).
One of the more popular voltage reference generators for generating a negative voltage reference signal for coupling to the inactive word lines includes a bandgap voltage reference. Typically, a bandgap voltage reference circuit uses the negative temperature coefficient of emitter-base voltage differential of two transistors operating at different current densities to make a zero temperature coefficient reference. Such an approach proved adequate until advances in sub-micron CMOS processes resulted in supply voltages being scaled-down with the present processes operating at sub 1 volt supply voltages. This trend presents a greater challenge in designing bandgap reference circuits which can operate at very low voltages. Even though conventional low-voltage bandgap circuits can generate a low voltage PVT insensitive voltage reference generator (e.g., approximately 0.6 V), the minimum Vcc required for proper operation at cold temperatures is approximately 1.05 V. Such a high minimum Vcc results from a high forward bias voltage of the PN diode junction.
FIG. 1 illustrates a conventional circuit diagram of a voltage reference generator 10 including a bandgap voltage reference 12 configured to generate a signal Vbandgap 14. The bandgap voltage reference 12 includes a differential amplifier 18 coupled on a first input to a divider network including a resistive (L*R) element 20 and a diode (1×) element 22. A second input of the differential amplifier 18 is coupled to a divider network including a resistive (L*R) element 24, resistive (R) element 26 and a diode array (8×) element 28. The signal Vbandgap 14 couples to a differential amplifier 30 and generates a reference signal 32. In the conventional voltage reference generator 10, the bandgap voltage reference 12 outputs the signal Vbandgap 14 with a potential of approximately 1.2 volts to 1.3 volts. The signal Vbandgap 14 goes through the differential amplifier 30 to generate the reference signal 32 having a potential of approximately −0.3 volts. The signal Vbandgap 14 must be set about 1.3 volts to get the zero temperature coefficient as shown by:(Vbandgap)=L*n*ln K*Vt+Vd1                where, L is the resistor ratio, n is the process constant (approx.=1), K is the BJT ratio, Vt is the thermal voltage (about 25.6 mV at room temp, has temp. coefficient of about 0.085 mV/C), and Vd1 is the voltage at the 1× diode (about 0.65 volts at 27° C., has temp. coefficient of about −2.2 mV/C).        In order to have a zero temperature coefficient, L*n*ln K*0.085 mV=2.2 mV, so the L*n*ln K must be about 2.2 mV/0.085 mV=25.8.        Thus, Vbandgap=25.8*25.6 mV+0.65=1.31 volts.Since the Vbandgap is about 1.3 volts, the minimum power supply voltage for the bandgap shown in FIG. 1 must be higher than 1.3 volts, which is unacceptable for circuits that operate on a Vcc of less than 1.2 volts.        
FIG. 2 illustrates another conventional circuit diagram of a voltage reference generator 50 which includes a bandgap voltage reference 52 which is configured to generate a signal Vbandgap 54. The bandgap voltage reference 52 includes a differential amplifier 58 coupled on a first input to a network including a resistive element 60 and a diode (1X) element 62. A second input of the differential amplifier 58 is coupled to a network including a resistive element 64 and a diode array (8X) element 66. The signal Vbandgap 54 couples to a unity buffer 68 and a differential amplifier 70 and generates a reference signal 72. In the conventional voltage reference generator 50, the CTAT current flows through a PTAT resistor 74 to generate a zero temperature coefficient signal Vbandgap 54 of about 0.6 volts. The voltage reference generator is then buffered and connected to the differential amplifier 70 to generate a −0.3 volt reference voltage. One disadvantage of this approach occurs during cold temperature operation when the voltage on the diode element 62 at the cold temperature becomes higher (e.g., about 0.82 volts at −40° C.). Accordingly, additional voltage (e.g., 0.2 volts to 0.3 volts) is needed for the PMOS devices in the amplifiers to remain in the saturation region. Thus, the minimum power supply voltage for the bandgap voltage reference 52 shown in FIG. 2 must be higher than 0.82 volts+0.23 volts=1.05 volts. Although the bandgap voltage reference 52 may output a lower potential for signal Vbandgap 54 than the conventional bandgap voltage reference 12 of FIG. 1, the minimum acceptable Vcc of the voltage reference generator 50 of FIG. 2 remains above 1.0 volts (e.g., 1.05 volts) which is unacceptable for circuits that desire to operate on a Vcc operating supply of less than 1.0 volt.
Therefore, what is needed is a method and apparatus for generating a reference signal that remains relatively stable for a broader range of operating voltages including lower operating potentials that would otherwise result in device operation outside of the saturation region of circuit devices.